This invention relates in general to the design, and automation thereof, of high-performance digital integrated circuits and in particular to the problem of accurate early estimation of circuit parasitics for hierarchical custom VLSI circuits.
In custom VLSI circuit design, the interconnect parasitic (either wire or via) between circuits in a design is typically manually measured or estimated based on a drawn floorplan of the design. These interconnect parasitic elements are then manually annotated onto the schematic. The schematic with the estimated interconnect parasitics is then analyzed through timing tools for timing and area optimization. The process requires significant manual effort on the part of the designer in measuring and estimating wire lengths between circuits in the design and then annotating the schematic with these parasitic elements. The accuracy and completeness of the estimated interconnect lengths between circuits depends upon the experience of the designer and can vary significantly within a large VLSI design team. Because of the time required, typically only a critical portion of the interconnect lengths are estimated, and thus, the timing of the design will not be known with a high degree of confidence until the circuit layout is completely routed and extracted timing is performed.
Chan et al. U.S. Patent Application US 2006/0190900, the disclosure of which is incorporated by reference herein, discloses a circuit design technique for automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout. A route estimator, such as Steiner estimation, is employed to estimate lengths of the interconnect segments based on the pin locations of a plurality of pins.
In the hierarchical circuit design flow, the traditional Steiner estimation typically tends to be pessimistic for nets that cross hierarchy, i.e., input/output (I/O) nets in all levels of the hierarchy below the top level. Pessimistic in this context means that the Steiner estimation overestimates the length of wiring due to, for example, redundant wiring interconnect segments. A typical method to avoid pessimistic parasitic estimation in a hierarchical design is to flatten the entire design into a single level which destroys the hierarchy and can be difficult for the designer to debug in case of a problem.